該程序?qū)W(xué)習(xí)和理解arm編程很有幫助.為了便于理解,這里我全部采用實(shí)際地址,不用宏定義.

程序語(yǔ)言為 arm 匯編,具體過(guò)程參考arm編程,具體寄存器接口定義參見(jiàn)arm硬件手冊(cè)

VramBaseAddress EQU 0xC0000000 ;DRAM起始地址,在arm硬件地址映射定義,見(jiàn)arm編程
Length1 EQU 0x100


FlashBase EQU 0x70000000 ;Flash的基地址,在Boot模式下,為0x70000000
MMUCP CP 15 ;協(xié)處理器15

AREA |C$$code|, CODE, READONLY

ENTRY

EXPORT main

main
MOV r14, #0x70 ;設(shè)置MMU無(wú)效, 32位模式, Little endian
MCR MMUCP, 0, r14, c1, c0, 0

MRS r14, CPSR
BIC r14, r14, #0x1f ;Mask
ORR r14, r14, #0xc0 + 0x13 ;關(guān)閉所有 IRQ FIQ, 用SVC32 模式
MSR CPSR, r14

LDR r11, =0x80000000 ;內(nèi)部寄存器基地址 0x80000000
LDR r12, =0x80001000

MOV r0, #0

STR r0, [r11, #0x280] ;disable 所有中斷
STR r0, [r12, #0x280]

LDR r0, =0x840100 ;在系統(tǒng)控制寄存器SYSCON1中
STR r0, [r11, #0x100] ;使能外部時(shí)鐘 EXCKEN 和串口 UART1

　
LDR r0, =0x06 ;在系統(tǒng)控制寄存器SYSCON2中
STR r0, [r12, #0x100] ;使能16-bit DRAM, 鍵盤KBD6

LDR r0, =0x03010100 ;在存儲(chǔ)控制寄存器MEMCFG1中
STR r0, [r11, #0x180] ;設(shè)置外設(shè)數(shù)據(jù)線寬度CS0:16位,CS1,2:32位,CS3:8位

;特別注意:

1. 如設(shè)置線寬為16位,由于CPU是32位,CPU會(huì)把32位數(shù)據(jù)分兩次操作寫入,每次寫16位,這樣對(duì)32位的外設(shè)來(lái)說(shuō)是一種浪費(fèi)

例如: LDR r0, =0x10000000
LDR r1, =0x12345678
STR r1,[r0]
實(shí)際情況是 第一次寫入地址0x10000000的數(shù)據(jù)是 0x1234
第二次寫入地址0x10000002的數(shù)據(jù)是 0x5678

示波器上觀察的情況是一個(gè)片選信號(hào)/CS低電平范圍內(nèi),有兩個(gè)寫入信號(hào)/WE低電平.

2. 如設(shè)置線寬為32位,CPU會(huì)把32位數(shù)據(jù)一次寫入,如果外設(shè)是16位的話,如ISA網(wǎng)卡,就會(huì)造成高16位丟失.

例如: LDR r0, =0x10000000
LDR r1, =0x12345678
STR r1,[r0]
實(shí)際情況是 一次寫入地址0x10000000的數(shù)據(jù)是 0x12345678

LDR r0, = 0xff ;DRAM刷新率refresh rate,設(shè)置要適當(dāng),否則數(shù)據(jù)丟失
STR r0, [r11, #0x200]

LDR r13, =0xc0020000 ;設(shè)置堆棧 Stack, r13 為arm定義的堆棧指針
;Init OK
LDR r0, =receiving_msg
BL printmsg

BL dram_test ;跳轉(zhuǎn)指令,執(zhí)行測(cè)試DRAM

LDR r0, =startloader_cmdmsg
BL printmsg

BL Beep

LDR r0, =0x60005 ;設(shè)置波特率 38400, 8位
LDR r11, =0x80000000
STR r0, [r11, #0x4c0] ;初始化串口 UART
;Receive data and save it to buffer ;開始接收數(shù)據(jù)
LDR r12, =SaveAddr ;First 8 bytes are start address and length
;Receive address
LDR r5, =0x4 ;Read first 4 bytes
MOV r0, #0
rx_loop1
LDR r1, [r11, #0x140] ;檢查系統(tǒng)狀態(tài)寄存器System Status Register 1
TST r1, #0x00400000 ;UART1 Rx 是否為空
BNE rx_loop1 ;等待數(shù)據(jù) Wait data
LDR r1, [r11, #0x480] ;讀數(shù)據(jù) Read data
AND r1, r1, #0xff
ORR r0, r1, r0, ROR #8
SUBS r5, r5, #1
BNE rx_loop1
MOV r0, r0, ROR #8

STR r0, [r12]
ADD r12, r12, #4

;Receive count
LDR r12, =Count
LDR r5, =0x4 ;Read second 4 bytes
MOV r0, #0
rx_loop2
LDR r1, [r11, #0x140] ;檢查系統(tǒng)狀態(tài)寄存器System Status Register 1
TST r1, #0x00400000 ;UART1 Rx 是否為空
BNE rx_loop2 ;等待數(shù)據(jù) Wait data
LDR r1, [r11, #0x480] ;讀數(shù)據(jù) Read data
AND r1, r1, #0xff
ORR r0, r1, r0, ROR #8
SUBS r5, r5, #1
BNE rx_loop2
MOV r0, r0, ROR #8

STR r0, [r12]
MOV r6, r0 ;Save the count to r6

;Receive data
MOV r5, r0
MOV r9, #0
LDR r10, =BufferBase
MOV r12, #0
rx_loop3
LDR r1, [r11, #0x140] ;System Status Register 1
TST r1, #0x00400000 ;UART1 Rx Empty
BNE rx_loop3 ;Wait data
LDR r1, [r11, #0x480] ;Read data
AND r1, r1, #0xff
STRB r1, [r10, r12]
ADD r12, r12, #1

nextbyte ;讀下一個(gè)字節(jié)
SUBS r5, r5, #1
BNE rx_loop3
;Receive data OK ;數(shù)據(jù)接收完畢

MOV r1, #0x31
BL send_char
MOV r1, #0x0d
BL send_char
MOV r1, #0x0a
BL send_char

;Save it to Flash ROM 把數(shù)據(jù)寫入Flash ROM