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高速數(shù)據(jù)轉(zhuǎn)換系統(tǒng)對(duì)時(shí)鐘和數(shù)據(jù)傳輸?shù)男阅芤?/p> </div> </div> </div>    <div class="pxkkcbx" id="container"> <section> <article> <h1>高速數(shù)據(jù)轉(zhuǎn)換系統(tǒng)對(duì)時(shí)鐘和數(shù)據(jù)傳輸?shù)男阅芤?/h1> <div id="cgupkij" class="authorTimeSource"> <span>作者：</span> <span>時(shí)間：2011-11-23</span> <span>來(lái)源：網(wǎng)絡(luò)</span> <link rel="stylesheet" type="text/css"/> <span style="float:right; width:130px;margin-right:0px; text-align:right;"> <div id="jyaoytu" class="nav0"> <ul> <li><a href="javascript:void(0);"><img src="http://cafeforensic.com/event/action/images/icon_add_4.png" width="20" border="0" align="absmiddle" />加入技術(shù)交流群</a> <ul> <li style="text-align:center;"><img src="http://cafeforensic.com/event/company/images/code_1.jpg" width="130"><br />掃碼加入<br />和技術(shù)大咖面對(duì)面交流<br />海量資料庫(kù)查詢</li> </ul> </li> </ul> </div> </span> <span style="float:right; width:30px;margin-right:0px; text-align:right;"><a rel="nofollow">收藏</a></span> </div> <div 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id="artcontent" sizset="2" sizcache="3"><p sizset="63" sizcache="1">隨著今天模數(shù)轉(zhuǎn)換器的數(shù)據(jù)轉(zhuǎn)換采樣速度進(jìn)入到每秒千兆次采樣(GSPS)，系統(tǒng)需要能夠支持這樣高的轉(zhuǎn)換速度，模擬器件必須產(chǎn)生和放大高頻信號(hào)。除了模擬信號(hào)路徑外，設(shè)計(jì)師需要完全了解采樣<a class="contentlabel" href="http://cafeforensic.com/news/listbylabel/label/時(shí)鐘"><em>時(shí)鐘</em></a>和高比特率數(shù)據(jù)獲取電路方面。信號(hào)路徑設(shè)計(jì)師將為這兩個(gè)關(guān)鍵的方面提供建議方案。下面的信息與需要高性能ADC的系統(tǒng)緊密相關(guān)。<br /><br /><strong><a class="contentlabel" href="http://cafeforensic.com/news/listbylabel/label/時(shí)鐘"><em>時(shí)鐘</em></a>源</strong><br /><br />在<a class="contentlabel" href="http://cafeforensic.com/news/listbylabel/label/高速數(shù)據(jù)"><em>高速數(shù)據(jù)</em></a><a class="contentlabel" href="http://cafeforensic.com/news/listbylabel/label/轉(zhuǎn)換系統(tǒng)"><em>轉(zhuǎn)換系統(tǒng)</em></a>中一個(gè)最重要的子系統(tǒng)是<a class="contentlabel" href="http://cafeforensic.com/news/listbylabel/label/時(shí)鐘"><em>時(shí)鐘</em></a>源，這是因?yàn)闀r(shí)鐘信號(hào)的時(shí)序準(zhǔn)確性可以直接影響ADC的動(dòng)態(tài)特性。為減少這種影響，ADC時(shí)鐘源必須表現(xiàn)出非常低的時(shí)序抖動(dòng)或相位噪聲。如果在選擇時(shí)鐘電路時(shí)沒(méi)有考慮到這種因素，無(wú)論前端模擬電路或者ADC的質(zhì)量有多高，系統(tǒng)可能表現(xiàn)出很差的動(dòng)態(tài)性能。優(yōu)良的時(shí)鐘將總能在精確的時(shí)鐘間隔內(nèi)出現(xiàn)時(shí)鐘沿的轉(zhuǎn)換。實(shí)際上，時(shí)鐘邊沿到達(dá)的時(shí)間間隙總是在不斷變化的，這種時(shí)序的不確定性帶來(lái)的結(jié)果是采樣波形的信噪比會(huì)受到數(shù)據(jù)轉(zhuǎn)換過(guò)程的影響。</p>本文引用地址：<a href="http://cafeforensic.com/article/187163.htm">http://cafeforensic.com/article/187163.htm</a><p align="center" sizset="2" sizcache="3"><img onload="if(this.width>620)this.width=620;" onclick="window.open(this.src)" style="cursor:pointer" class="scaleImage" height="129" src="http://editerupload.eepw.com.cn/fetch/20131113/187163_1_0.jpg" width="250" alt="" /></p><p> 圖1：PLL與VCO時(shí)鐘系統(tǒng)。<br /><br />可以容忍的最大時(shí)鐘抖動(dòng)為抖動(dòng)噪聲超過(guò)量化噪聲(1/2LSB)前的時(shí)鐘抖動(dòng)。這可以用下面的公式定義：</p><p align="center" sizset="3" sizcache="3"><img onload="if(this.width>620)this.width=620;" onclick="window.open(this.src)" style="cursor:pointer" class="scaleImage" height="73" src="http://editerupload.eepw.com.cn/fetch/20131113/187163_1_1.jpg" width="501" alt="" /></p><p>如果優(yōu)化輸入電壓(VIN)使之等于ADC的輸入電壓范圍(VINFSR)，那么抖動(dòng)要求成為ADC分辨率(N位)和被采樣的輸入頻率(fin)的一個(gè)因子。<br />對(duì)于達(dá)到奈奎斯特速率(對(duì)于1GSPS轉(zhuǎn)換速率為500MHz)的輸入頻率，總的抖動(dòng)要求是：</p><p align="center" sizset="4" sizcache="3"><img onload="if(this.width>620)this.width=620;" onclick="window.open(this.src)" style="cursor:pointer" class="scaleImage" height="62" src="http://editerupload.eepw.com.cn/fetch/20131113/187163_1_2.jpg" width="423" alt="" /></p><p align="center" sizset="5" sizcache="3"><img onload="if(this.width>620)this.width=620;" onclick="window.open(this.src)" style="cursor:pointer" class="scaleImage" height="58" src="http://editerupload.eepw.com.cn/fetch/20131113/187163_1_3.jpg" width="203" alt="" /></p><p>這個(gè)值代表了來(lái)自所有抖動(dòng)源的總抖動(dòng)。ADC器件本身導(dǎo)致的一個(gè)抖動(dòng)源稱為窗口抖動(dòng)(aperture jitter)，這是輸入采樣和器件的保持電路相關(guān)的一種時(shí)序不確定性，在確定時(shí)鐘源允許的最大時(shí)鐘抖動(dòng)時(shí)，需要考慮這種不確定性。</p><p>時(shí)鐘電路抖動(dòng)=(Tj(rms)2-(ADC(窗口抖動(dòng))2))1/2</p><p>以ADC08D1000為例，窗口抖動(dòng)在數(shù)據(jù)手冊(cè)中給定的值為0.4ps，這個(gè)值將ADC時(shí)鐘的抖動(dòng)標(biāo)準(zhǔn)限制到-1.1ps。<br /><br />然而，當(dāng)用在數(shù)據(jù)<a class="contentlabel" href="http://cafeforensic.com/news/listbylabel/label/轉(zhuǎn)換系統(tǒng)"><em>轉(zhuǎn)換系統(tǒng)</em></a>中時(shí)，將振蕩器的性能數(shù)據(jù)與規(guī)范要求簡(jiǎn)單地匹配或許并不足以獲得期望的結(jié)果。這是因?yàn)轭l率分量也扮演著重要的作用。因此，用頻譜分析儀來(lái)對(duì)時(shí)鐘信號(hào)進(jìn)行檢查很重要，并確保與基本頻率相關(guān)的能量沒(méi)有在很大的范圍內(nèi)擴(kuò)展。延伸到更高頻率的毛刺可能很明顯，也將會(huì)對(duì)性能產(chǎn)生直接的影響。<br /><br />圖1顯示了針對(duì)ADC08D1000的推薦時(shí)鐘電路，由一個(gè)鎖相環(huán)器件(LMX2312)連接到可變電感壓控振蕩器(VCO)組成。PLL和VCO維持達(dá)到奈奎斯特輸入頻率ADC08D1000要求的信噪比(46dB)。<br /><br /><strong>數(shù)據(jù)獲取</strong><br /><br />對(duì)信號(hào)進(jìn)行高頻(1GSPS及以上)采樣意味著轉(zhuǎn)換所產(chǎn)生的數(shù)字輸出數(shù)據(jù)必須儲(chǔ)存起來(lái)，或者至少快速地轉(zhuǎn)移。處理每秒超過(guò)一億次轉(zhuǎn)換的兩個(gè)關(guān)鍵問(wèn)題是系統(tǒng)中數(shù)字器件之間的信號(hào)完整性，以及每個(gè)時(shí)鐘周期數(shù)據(jù)轉(zhuǎn)移的速度。<br />為使數(shù)字輸出信號(hào)完整性最大化，高速ADC使用低電壓差分信號(hào)(或者LVDS)傳輸(見(jiàn)圖2)。</p><p align="center" sizset="6" sizcache="3"><img onload="if(this.width>620)this.width=620;" onclick="window.open(this.src)" style="cursor:pointer" class="scaleImage" height="238" src="http://editerupload.eepw.com.cn/fetch/20131113/187163_1_4.jpg" width="519" alt="" /></p><p> 圖2：典型的LVDS電路。<br /><br />LVDS信號(hào)傳輸方法的主要優(yōu)點(diǎn)是以非常低的功率預(yù)算實(shí)現(xiàn)高數(shù)據(jù)速率，對(duì)每個(gè)將通過(guò)一個(gè)電路板或者電纜傳輸?shù)姆蛛x信號(hào)采用兩條連線來(lái)實(shí)現(xiàn)這種低功耗。每條線上的電壓變化的方向互相相反，且與像CMOS或者TTL這樣的單端信號(hào)相比信號(hào)的強(qiáng)度比較小(一般為350mV)。這是因?yàn)椴罘蛛娐饭逃械目乖肼暷芰?，因此可以使用低電壓擺幅信號(hào)。這反過(guò)來(lái)意味著信號(hào)頻率可以更快，因?yàn)樾盘?hào)的上升時(shí)間更短了。<br /><br />電路板上傳輸差分波形的信號(hào)線應(yīng)該設(shè)計(jì)成具有100Ω的特征阻抗(LVDS標(biāo)準(zhǔn)所定義的值)，這些線在接收器端用100Ω的電阻來(lái)進(jìn)行端接以與線路匹配。通過(guò)發(fā)射器電路上的電流源在100Ω的電阻上流過(guò)3.5mA的電流，產(chǎn)生一個(gè)信號(hào)電壓，提供350mV的信號(hào)擺幅，供接收電路檢測(cè)。<br /><br />高速發(fā)送數(shù)據(jù)只是問(wèn)題的一半，還需要考慮將數(shù)據(jù)存儲(chǔ)在存儲(chǔ)器陣列中以作后<br />續(xù)處理。ADC對(duì)其每個(gè)通道提供一個(gè)解復(fù)用的數(shù)據(jù)輸出。器件不是提供一個(gè)運(yùn)行在等于采樣速度的單一8位總線，而是同時(shí)在兩個(gè)8位數(shù)據(jù)總線上輸出兩個(gè)連續(xù)采樣。這種方法將數(shù)據(jù)速率減半，但是增加了數(shù)據(jù)位數(shù)，對(duì)于一個(gè)1GSPS的采樣速率，來(lái)自ADC的轉(zhuǎn)換數(shù)據(jù)輸出速度為500MHz。即使在這種降低的速度下，大多數(shù)分立存儲(chǔ)器或者FPGA內(nèi)部存儲(chǔ)器在可靠獲取這個(gè)數(shù)據(jù)上也存在問(wèn)題。因此使用DDR非常有利，因?yàn)镈DR在時(shí)鐘的上升和下降沿都輸出數(shù)據(jù)。盡管數(shù)據(jù)速率對(duì)于DDR信號(hào)傳輸來(lái)說(shuō)不變，時(shí)鐘頻率減半，達(dá)到更便于管理的250MHz，這個(gè)頻率在CMOS存儲(chǔ)電路的范圍內(nèi)。在數(shù)據(jù)能保存在存儲(chǔ)器之前，需要在輸入到FPGA器件中間采用一個(gè)數(shù)據(jù)鎖存器對(duì)。第一個(gè)鎖存器使用同步數(shù)據(jù)時(shí)鐘，而第二個(gè)鎖存器使用180度異相的時(shí)鐘，或者反向數(shù)據(jù)時(shí)鐘(見(jiàn)圖3)。</p><p align="center" sizset="7" sizcache="3"><img onload="if(this.width>620)this.width=620;" onclick="window.open(this.src)" style="cursor:pointer" class="scaleImage" height="449" src="http://editerupload.eepw.com.cn/fetch/20131113/187163_1_5.jpg" width="472" alt="" /></p><p>圖3：FPGA數(shù)據(jù)獲取架構(gòu)框圖。<br /><br />為簡(jiǎn)化這種時(shí)鐘要求，F(xiàn)PGA帶有一種以PLL(鎖相環(huán))或者DLL(延時(shí)鎖定環(huán))形式實(shí)現(xiàn)的數(shù)字時(shí)鐘管理器。這些器件允許在內(nèi)部產(chǎn)生時(shí)鐘信號(hào)，這些時(shí)鐘信號(hào)能與輸入時(shí)鐘信號(hào)鎖定，提供相位延時(shí)間隔為0、90、180和270度。這種時(shí)鐘管理功能允許DDR時(shí)鐘方案通過(guò)提供一種精確的180度移相時(shí)鐘來(lái)有效工作。這反過(guò)來(lái)允許輸入數(shù)據(jù)與下降沿同步，以能可靠地獲取到數(shù)據(jù)鎖存器中。<br />在鎖存之后，輸入數(shù)據(jù)可以被傳輸?shù)紽IFO存儲(chǔ)器或者Block RAM。在這里，數(shù)據(jù)可以以很低的速度輕易地被系統(tǒng)微控制器獲得，以進(jìn)行獲取后的處理。</p></div></span>  <div class="gjznqxf" id="coverDiv" class="article_reg" style="width:100%;overflow:hidden;display:none;z-index:10;position:absolute;left:0;background:#fff;"> <center> <img src="https://webstorage.eepw.com.cn/images/display/reg.jpg" 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