基于ARM+FPGA控制的LTC2207采集應(yīng)用
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采用硬件描述語(yǔ)言VerilogHDL，對(duì)LTC2207相關(guān)引腳的使能以及FPGA如何讀取采集來(lái)的數(shù)據(jù)的程序如下：
always @(posedge clk or negedge rst_n)
if(!rst_n)
begin
/OE2_2207 = 1b0;//相關(guān)引腳的軟件配置
MODE2_2207 = 1b1;
RAND2_2207 = 1b0;
PGA2_2207 = 1b0;
DITH2_2207 = 1b1;
SHDN2_2207 = 1b0;
DATA2_receive = 16d0;
state = IDLE;
done2 = 1b0;
end
else
begin
case(state)
IDLE: if(start_reg)
begin
en_9150 =1;
state = READ_DATA;
end
READ_DATA:
begin//FPGA讀取采集來(lái)的數(shù)據(jù)
en_9150 =0;
if(CLKp2_2207_reg)
begin
DATA2_receive = DATA2_2207;
done2 = 1b1;
state = IDLE;
end
else
done2 = 1b1;
end
default: ;
endcase
end
與S3C2440 GPJ1口連接的FPGA端的start控制程序代碼如下[3]：
always @(posedge clk or negedge rst_n)
if(!rst_n)
begin
start_reg1 = 0;
start_reg2 = 0;
end
else
begin
start_reg1 = start;
start_reg2 = start_reg1;
end
assign start_reg = start_reg1 (～start_reg2);
S3C2440控制啟動(dòng)FPGA開(kāi)始采集的start程序如下[4]：
#include
#include 2440addr.h
#include 2440lib.h
#include def.h
#include fpga.h
void delay(int a) {//延遲
int k;
for(k=0;k
}
void start(){
rGPJCON=(12)+(06); //設(shè)置I/O口GPJ1為輸出屬性，GPJ3為輸入屬性
rGPJUP=0x1fff;//禁止GPJ端口的上拉
rGPJDAT=(01);//初始化時(shí)置低電平
while(1) {
rGPJDAT=(11);//GPJ1置高
delay(50);
rGPJDAT=(01);//GPJ1置低
delay(500);
}
}
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