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          EEPW首頁(yè) > 嵌入式系統(tǒng) > 設(shè)計(jì)應(yīng)用 > STM32中關(guān)于Contex-M3寄存器說(shuō)明

          STM32中關(guān)于Contex-M3寄存器說(shuō)明

          作者: 時(shí)間:2016-11-11 來(lái)源:網(wǎng)絡(luò) 收藏
          STM32中用到了Cortex-M3定義的三組寄存器,有關(guān)這三組寄存器的說(shuō)明不在STM32的技術(shù)手冊(cè)中,需要參考ARM公司發(fā)布的Cortex-M3 Technical Reference Manual (r2p0)。

          在STM32的固件庫(kù)中定義了三個(gè)結(jié)構(gòu)體與這三個(gè)寄存器組相對(duì)應(yīng),這三個(gè)結(jié)構(gòu)體與ARM手冊(cè)中寄存器的對(duì)應(yīng)關(guān)系如下:

          本文引用地址:http://cafeforensic.com/article/201611/316983.htm


          一、NVIC寄存器組
          STM32的固件庫(kù)中有如下定義:
          typedef struct
          {
          vu32 ISER[2];
          u32 RESERVED0[30];
          vu32 ICER[2];
          u32 RSERVED1[30];
          vu32 ISPR[2];
          u32 RESERVED2[30];
          vu32 ICPR[2];
          u32 RESERVED3[30];
          vu32 IABR[2];
          u32 RESERVED4[62];
          vu32 IPR[11];
          } NVIC_TypeDef;

          它們對(duì)應(yīng)ARM手冊(cè)中的名稱為
          ISER = Interrupt Set-Enable Registers
          ICER = Interrupt Clear-Enable Registers
          ISPR = Interrupt Set-Pending Register
          ICPR = Interrupt Clear-Pending Register
          IABR = Active Bit Register
          IPR = Interrupt Priority Registers

          每個(gè)寄存器有240位,以Interrupt Set-Enable Registers說(shuō)明,ISER[0]對(duì)應(yīng)中斷源0~31,ISER[1]對(duì)應(yīng)中斷源32~63,STM32只有60個(gè)中斷源,所以沒有ISER[2:7]。

          參考STM32技術(shù)參考手冊(cè)中的中斷向量表,中斷源的位置為:
          位置0 - WWDG = Window Watchdog interrupt
          位置1 - PVD = PVD through EXTI Line detection interrupt
          位置2 - TAMPER = Tamper interrupt
          ......
          位置58 - DMA2_Channel3 = DMA2 Channel3 global interrupt
          位置59 - DMA2_Channel4_5 = DMA2 Channel4 and DMA2 Channel5 global interrupts

          二、系統(tǒng)控制寄存器組
          STM32的固件庫(kù)中有如下定義:
          typedef struct
          {
          vuc32 CPUID;
          vu32 ICSR;
          vu32 VTOR;
          vu32 AIRCR;
          vu32 SCR;
          vu32 CCR;
          vu32 SHPR[3];
          vu32 SHCSR;
          vu32 CFSR;
          vu32 HFSR;
          vu32 DFSR;
          vu32 MMFAR;
          vu32 BFAR;
          vu32 AFSR;
          } SCB_TypeDef; /* System Control Block Structure */

          它們對(duì)應(yīng)ARM手冊(cè)中的名稱為
          CPUID = CPUID Base Register
          ICSR = Interrupt Control State Register
          VTOR = Vector Table Offset Register
          AIRCR = Application Interrupt/Reset Control Register
          SCR = System Control Register
          CCR = Configuration Control Register
          SHPR = System Handlers Priority Register
          SHCSR = System Handler Control and State Register
          CFSR = Configurable Fault Status Registers
          HFSR = Hard Fault Status Register
          DFSR = Debug Fault Status Register
          MMFAR = Mem Manage Address Register
          BFAR = Bus Fault Address Register
          AFSR = Auxiliary Fault Status Register

          三、系統(tǒng)時(shí)鐘寄存器組
          STM32的固件庫(kù)中有如下定義:
          typedef struct
          {
          vu32 CTRL;
          vu32 LOAD;
          vu32 VAL;
          vuc32 CALIB;
          } SysTick_TypeDef;

          它們對(duì)應(yīng)ARM手冊(cè)中的名稱為
          CTRL = SysTick Control and Status Register
          LOAD = SysTick Reload Value Register
          VAL = SysTick Current Value Register
          CALIB = SysTick Calibration Value Register



          關(guān)鍵詞: STM32Contex-M3寄存

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