#ifndef __STM32F10x_H#define __STM32F10x_H#ifdef __cplusplusextern "C" {#endif

#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL) /* #define STM32F10X_LD */     /*!< STM32F10X_LD: STM32 Low density devices *//* #define STM32F10X_LD_VL */  /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */  /* #define STM32F10X_MD */     /*!< STM32F10X_MD: STM32 Medium density devices *//* #define STM32F10X_MD_VL */  /*!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */  /* #define STM32F10X_HD */     /*!< STM32F10X_HD: STM32 High density devices *//* #define STM32F10X_HD_VL */  /*!< STM32F10X_HD_VL: STM32 High density value line devices */  /* #define STM32F10X_XL */     /*!< STM32F10X_XL: STM32 XL-density devices *//* #define STM32F10X_CL */     /*!< STM32F10X_CL: STM32 Connectivity line devices */#endif#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL)#error "Please select first the target STM32F10x device used in your application (in stm32f10x.h file)"#endif

#if !defined  USE_STDPERIPH_DRIVER/*** @brief Comment the line below if you will not use the peripherals drivers.In this case, these drivers will not be included and the application code will be based on direct access to peripherals registers *//*#define USE_STDPERIPH_DRIVER*/#endif

/*** @brief In the following line adjust the value of External High Speed oscillator (HSE)used in your application Tip: To avoid modifying this file each time you need to use different HSE, youcan define the HSE value in your toolchain compiler preprocessor.*/           #if !defined  HSE_VALUE#ifdef STM32F10X_CL   #define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */#else #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */#endif /* STM32F10X_CL */#endif /* HSE_VALUE */

/*** @brief In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value */#define HSE_STARTUP_TIMEOUT   ((uint16_t)0x0500) /*!< Time out for HSE start up */#define HSI_VALUE    ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/

/*** @brief STM32F10x Standard Peripheral Library version number*/#define __STM32F10X_STDPERIPH_VERSION_MAIN   (0x03) /*!< [31:24] main version */                                  #define __STM32F10X_STDPERIPH_VERSION_SUB1   (0x05) /*!< [23:16] sub1 version */#define __STM32F10X_STDPERIPH_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */#define __STM32F10X_STDPERIPH_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ #define __STM32F10X_STDPERIPH_VERSION       ( (__STM32F10X_STDPERIPH_VERSION_MAIN << 24)|(__STM32F10X_STDPERIPH_VERSION_SUB1 << 16)|(__STM32F10X_STDPERIPH_VERSION_SUB2 << 8)|(__STM32F10X_STDPERIPH_VERSION_RC))

/*** @brief Configuration of the Cortex-M3 Processor and Core Peripherals */#ifdef STM32F10X_XL#define __MPU_PRESENT             1 /*!< STM32 XL-density devices provide an MPU */#else#define __MPU_PRESENT             0 /*!< Other STM32 devices does not provide an MPU */#endif /* STM32F10X_XL */#define __NVIC_PRIO_BITS          4 /*!< STM32 uses 4 Bits for the Priority Levels    */#define __Vendor_SysTickConfig    0 /*!< Set to 1 if different SysTick Config is used */

/*** @brief STM32F10x Interrupt Number Definition, according to the selected device *        in @ref Library_configuration_section */typedef enum IRQn{/******  Cortex-M3 Processor Exceptions Numbers ***************************************************/NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                             */MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt              */BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                      */UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                    */SVCall_IRQn                 = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                       */DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                 */PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                       */SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                   *//******  STM32 specific Interrupt Numbers *********************************************************/WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                            */PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt            */TAMPER_IRQn                 = 2,      /*!< Tamper Interrupt                                     */RTC_IRQn                    = 3,      /*!< RTC global Interrupt                                 */FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                               */RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                 */EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                 */EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                 */EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                 */EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                 */EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                 */DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                      */DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                      */DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                      */DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                      */DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                      */DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                      */DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                      */#ifdef STM32F10X_LD...#endif /* STM32F10X_LD */  #ifdef STM32F10X_LD_VL...#endif /* STM32F10X_LD_VL */#ifdef STM32F10X_MD...#endif /* STM32F10X_MD */  #ifdef STM32F10X_MD_VL...#endif /* STM32F10X_MD_VL */#ifdef STM32F10X_HD...#endif /* STM32F10X_HD */  .........} IRQn_Type;

@addtogroup Exported_types/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */typedef int32_t  s32;typedef int16_t s16;typedef int8_t  s8;typedef const int32_t sc32;  /*!< Read Only */typedef const int16_t sc16;  /*!< Read Only */typedef const int8_t sc8;   /*!< Read Only */typedef __IO int32_t  vs32;typedef __IO int16_t  vs16;typedef __IO int8_t   vs8;typedef __I int32_t vsc32;  /*!< Read Only */typedef __I int16_t vsc16;  /*!< Read Only */typedef __I int8_t vsc8;   /*!< Read Only */typedef uint32_t  u32;typedef uint16_t u16;typedef uint8_t  u8;typedef const uint32_t uc32;  /*!< Read Only */typedef const uint16_t uc16;  /*!< Read Only */typedef const uint8_t uc8;   /*!< Read Only */typedef __IO uint32_t  vu32;typedef __IO uint16_t vu16;typedef __IO uint8_t  vu8;typedef __I uint32_t vuc32;  /*!< Read Only */typedef __I uint16_t vuc16;  /*!< Read Only */typedef __I uint8_t vuc8;   /*!< Read Only */typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;/*!< STM32F10x Standard Peripheral Library old definitions (maintained for legacy purpose) */#define HSEStartUp_TimeOut   HSE_STARTUP_TIMEOUT#define HSE_Value            HSE_VALUE#define HSI_Value            HSI_VALUE

/* @addtogroup Peripheral_registers_structures  */  /** * @brief Analog to Digital Converter  */typedef struct{} ADC_TypeDef;/** * @brief Backup Registers  */typedef struct{} BKP_TypeDef;/** * @brief Controller Area Network TxMailBox */typedef struct{} CAN_TxMailBox_TypeDef;/** * @brief Controller Area Network FIFOMailBox */typedef struct{} CAN_FIFOMailBox_TypeDef;/** * @brief Controller Area Network FilterRegister */typedef struct{} CAN_FilterRegister_TypeDef;/** * @brief Controller Area Network */typedef struct{} CAN_TypeDef;/** * @brief Consumer Electronics Control (CEC)*/typedef struct{} CEC_TypeDef;/** * @brief CRC calculation unit */typedef struct{} CRC_TypeDef;/** * @brief Digital to Analog Converter*/typedef struct{} DAC_TypeDef;/** * @brief Debug MCU*/typedef struct{}DBGMCU_TypeDef;/** * @brief DMA Controller*/typedef struct{} DMA_Channel_TypeDef;typedef struct{} DMA_TypeDef;/** * @brief Ethernet MAC*/typedef struct{} ETH_TypeDef;/** * @brief External Interrupt/Event Controller*/typedef struct{} EXTI_TypeDef;/** * @brief FLASH Registers*/typedef struct{} FLASH_TypeDef;/** * @brief Option Bytes Registers*/typedef struct{} OB_TypeDef;/** * @brief Flexible Static Memory Controller*/typedef struct{} FSMC_Bank1_TypeDef; /** * @brief Flexible Static Memory Controller Bank1E*/typedef struct{} FSMC_Bank1E_TypeDef;/** * @brief Flexible Static Memory Controller Bank2*/typedef struct{} FSMC_Bank2_TypeDef;  /** * @brief Flexible Static Memory Controller Bank3*/typedef struct{} FSMC_Bank3_TypeDef; /** * @brief General Purpose I/O*/typedef struct{} GPIO_TypeDef;/** * @brief Alternate Function I/O*/typedef struct{} AFIO_TypeDef;/** * @brief Inter Integrated Circuit Interface*/typedef struct{} I2C_TypeDef;/** * @brief Independent WATCHDOG*/typedef struct{} IWDG_TypeDef;/** * @brief Power Control*/typedef struct{} PWR_TypeDef;/** * @brief Reset and Clock Control*/typedef struct{} RCC_TypeDef;/** * @brief Real-Time Clock*/typedef struct{} RTC_TypeDef;/** * @brief SD host Interface*/typedef struct{} SDIO_TypeDef;/** * @brief Serial Peripheral Interface*/typedef struct{} SPI_TypeDef;/** * @brief TIM*/typedef struct{} TIM_TypeDef;/** * @brief Universal Synchronous Asynchronous Receiver Transmitter*/typedef struct{} USART_TypeDef;/** * @brief Window WATCHDOG*/typedef struct{} WWDG_TypeDef;

/** @addtogroup Peripheral_memory_map* @{*/#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */#define SRAM_BB_BASE          ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */#define FSMC_R_BASE           ((uint32_t)0xA0000000) /*!< FSMC registers base address *//*!< Peripheral memory map */#define APB1PERIPH_BASE       PERIPH_BASE#define APB2PERIPH_BASE       (PERIPH_BASE + 0x10000)#define AHBPERIPH_BASE        (PERIPH_BASE + 0x20000)#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)....../** @addtogroup Peripheral_declaration* @{*/  #define TIM2                ((TIM_TypeDef *) TIM2_BASE)#define TIM3                ((TIM_TypeDef *) TIM3_BASE)#define TIM4                ((TIM_TypeDef *) TIM4_BASE)#define TIM5                ((TIM_TypeDef *) TIM5_BASE)#define TIM6                ((TIM_TypeDef *) TIM6_BASE)......

#ifdef USE_STDPERIPH_DRIVER#include "stm32f10x_conf.h"#endif

/** @addtogroup Exported_macro* @{*/#define SET_BIT(REG, BIT)     ((REG) |= (BIT))#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))#define READ_BIT(REG, BIT)    ((REG) & (BIT))#define CLEAR_REG(REG)        ((REG) = (0x0))#define WRITE_REG(REG, VAL)   ((REG) = (VAL))#define READ_REG(REG)         ((REG))#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))

#ifdef __cplusplus}#endif#endif /* __STM32F10x_H */