代碼：

key = 14;

mpll_val = (92<<12)|(1<<4)|(1);

ChangeMPllValue((mpll_val>>12)&0xff, (mpll_val>>4)&0x3f, mpll_val&3);

ChangeClockDivider(key, 12);

cal_cpu_bus_clk();

void ChangeMPllValue(int mdiv,int pdiv,int sdiv)

{

rMPLLCON = (mdiv<<12) | (pdiv<<4) | sdiv;

}

void ChangeClockDivider(int hdivn_val,int pdivn_val)

{

int hdivn=2, pdivn=0;

// hdivn_val (FCLK:HCLK)ratio hdivn

// 11 1:1 (0)

// 12 1:2 (1)

// 13 1:3 (3)

// 14 1:4 (2)

// pdivn_val (HCLK:PCLK)ratio pdivn

// 11 1:1 (0)

// 12 1:2 (1)

switch(hdivn_val) {

case 11: hdivn=0; break;

case 12: hdivn=1; break;

case 13:

case 16: hdivn=3; break;

case 14:

case 18: hdivn=2; break;

}

switch(pdivn_val) {

case 11: pdivn=0; break;

case 12: pdivn=1; break;

}

//Uart_Printf("Clock division change [hdiv:%x, pdiv:%x]n", hdivn, pdivn);

rCLKDIVN = (hdivn<<1) | pdivn;

switch(hdivn_val) {

case 16: // when 1, HCLK=FCLK/8.

rCAMDIVN = (rCAMDIVN & ~(3<<8)) | (1<<8);

break;

case 18: // when 1, HCLK=FCLK/6.

rCAMDIVN = (rCAMDIVN & ~(3<<8)) | (1<<9);

break;

}

if(hdivn!=0)

MMU_SetAsyncBusMode();

else

MMU_SetFastBusMode();

}

參考數(shù)據(jù)手冊(cè)：FIN=12000000 MDIV=92 PDIV=1 SDIV = 1 m=100,p=3,s=1, HSIVN=2 PDIVN =1 ,

根據(jù)MPLL的計(jì)算公式 2×100×1200000/（3×2）=400MHZ 即FCLK=400M

HCLK=FCLK/4=100M , PCLK=HCLK/2