M-PHY_資料下載

MIPI D-PHY 一致性解決方案

積分：0分 MIPI D-PHY 一致性解決方案泰克 |

nakey

MIPI D-PHY 物理層一致性測(cè)試

積分：0分 MIPI D-PHY 物理層一致性測(cè)試泰克 |

nakey

MIPI spec

積分：0分 D-PHY Specification |

zhuanjifen

MIPI DSI/CSI測(cè)試方案

積分：0分 MIPI-D-PHY 測(cè)試 |

zhuanjifen

mipi 顯示屏接口文檔

積分：0分 D-PHY Specification v01-00-00 |

zhuanjifen

78Q8430布板指南

積分：0分 Maxim 10BASE-T 100BASE-TX Fast Ethernet media-access controller MAC PHY transceiver Teridian |

soothmusic

【用戶指南】Altera收發(fā)器PHY IP核用戶指南(Altera Transceiver PHY IP Core User Guide)

積分：0分 Altera transceiver xcvr SERDES TX RX 10GBASE-R XAUI Interlaken PCI Express PIPE custom low latency deterministic latency PHY IP core |

【用戶指南】ALTDLL和ALTDQ_DQS宏功能模塊用戶指南(ALTDLL and ALTDQ_DQS Megafunctions User Guide)

積分：0分 Altera ALTDLL ALTDQ_DQS DQ DQS DLL delay-locked loops custom PHY custom interfaces delay chain setting phase offset control |

【用戶指南】10Gbps以太網(wǎng)媒體訪問(wèn)控制器宏功能模塊用戶指南(10-Gbps Ethernet MAC MegaCore Function User Guide)

積分：0分 Altera 10 gigabit 10gb Ethernet 10-Gbps Ethernet Media Access Controller IP core 10GbE MAC IEEE 802.3-2005 IEEE 802.1Qbb XAUI PHY 10GBASE-R |

【應(yīng)用筆記】AN328:Stratix II、Stratix II GX、and Arria GX器件和DDR2 SDRAM的接口(AN 328: Interfacing DDR2 SDRAM with Stratix II, Stratix II GX, and Arria GX Devices)

積分：0分 Altera FPGA ddr2 sdram interface memory interface design flow example walkthrough legacy data path architecture altmemphy megacore legacy phy board level simulation stratix ii stratix ii gx arria |

【應(yīng)用筆記】10Gpbs以太網(wǎng)MAC和XAUI PHY互操作性硬件演示參考設(shè)計(jì)(10-Gbps Ethernet MAC and XAUI PHY Interoperability Hardware Demonstration Reference Design)

積分：0分 Altera 10GbE 10GbE MAC bcm8727 broadcom ethernet PHY XAUI XAUI PHY Dual XAUI to SFP+ HSMC |

【應(yīng)用筆記】AN359:POS-PHY Level 4 MegaCore功能模塊參數(shù)選擇計(jì)算器(AN 359: POS-PHY Level 4 MegaCore Function Parameter Selection Calculator)

積分：0分 Altera POS-PHY Level 4 MegaCore |

【應(yīng)用筆記】PCI Express宏功能函數(shù)的外部PHY支持(External PHY Support in PCI Express MegaCore Functions)

積分：0分 Altera FPGA PCI Express PHY MegaCore |

【應(yīng)用筆記】AN462:使用ALTMEMPH宏功能模塊實(shí)現(xiàn)多存儲(chǔ)器接口(AN 462: Implementing Multiple Memory Interfaces Using the ALTMEMPHY Megafunction)

積分：0分 Altera FPGA ALTMEMPHY multiple memory interfaces PHY |

【應(yīng)用手冊(cè)】 AN 606: POS-PHY Level 4 (SPI-4.2) Loopback Reference Design

積分：0分 Altera FPGA POS-PHY Stratix IV Stratix III |

eSATA的測(cè)量方法

積分：0分 Maxim SAS SATA eSATA PHY testing eye diagrams jitter measurements SATA measurement eSATA measurement measurement methodology |

soothmusic

【應(yīng)用手冊(cè)】Single-Port Triple-Speed Ethernet and On-Board PHY Chip Reference Design

積分：0分 Altera FPGA Single-Port Triple-Speed Ethernet On-Board PHY Chip |

【應(yīng)用手冊(cè)】Implementing the CPRI Protocol using the Deterministic Latency Transceiver PHY IP Core

積分：0分 Altera FPGA PHY IP Core CPRI Protocol Stratix V Arria V |

工業(yè)以太網(wǎng)解決方案

積分：0分 Altera FPGA 以太網(wǎng) PHY |

Stratix V 器件Interlaken PHY IP 設(shè)計(jì)流程

積分：0分 Altera Stratix V Interlaken PHY IP FPGA |

Teranetics采用泰克儀器驗(yàn)證首個(gè)雙端口10GBASE-T PHY

積分：0分 TekTronix 10GBASE-T PHY |

ylzhjy

約束并分析Stratix IV, Stratix III, Arria II GX和Cyclone III器件外部存儲(chǔ)器接口時(shí)序

積分：0分 Altera Stratix IV Stratix III Arria II GX Cyclone III FPGA 外部存儲(chǔ)器接口 PHY |

usb2代碼

積分：0分 USB IP Core IOs HW SSRAM UTMI PHY Software Model |

an360 設(shè)計(jì)仿真模型for the POS-PHY Level 4 MegaCore

積分：0分 Altera Updating Simulation Models POS-PHY PLL LVDS RTL |

ASIC to FPGA 設(shè)計(jì)方法和指導(dǎo)

積分：0分 Altera ASIC FPGA EDA PHY SPOC Quartus Ⅱ |

WiFi vs. WiMAX 個(gè)人收集之研究論文資料2

積分：0分 WiMAX WiFi PHY MAC CSMA 802.16 QoS |

Updating Simulation Models for the POS-PHY Level 4 MegaCore Function

積分：0分 POS-PHY Level 4 MegaCore Function Simulation Model |

DS80C400 and PHY Reset

積分：0分 DS80C400 PHY RXCLK |

Xilinx嵌入式雜志第二期

積分：0分 Xilinx FPGA PHY |

速度高達(dá)54Mbps的IEEE802.11a無(wú)線LAN協(xié)議

積分：0分 The Institute of Electrical and Electronics Engineers Wireless LAN Medium Access Control PHY |